Scheduling, Compaction and Binding in a Retargetable Code Generator using Constraint Logic Programming

Code generation for embedded programmable processors is becoming increasingly important. Many of these processors have irregular architectures and offer instruction-level parallelism (e.g. DSPs). In order to generate code for a wide range of architectures, a code generator should be retargetable. Most of the previous code generation approaches concentrate on the datapath, not taking the peculiarities of the controller into account. The controller can have strange address generation schemes and imposes restrictions on the amount of parallelism in the datapath. In this paper we propose a new method to model all these restrictions and characteristics of the controller uniformly, in order to perform scheduling, compaction and binding in a retargetable code generator. For this, we exploit the programming paradigm of constraint logic programming (CLP). CLP offers a general and uniform model for various constraints, performs consistency checks, and integrates constraint solving techniques.